1. Technical Field
The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same.
2. Related Art
An example of semiconductor integrated circuits so far developed can be found in Japanese Laid-open patent publication No. 2004-55954. In the semiconductor integrated circuit according to this document, a capacitor is provided as a fill-cell capacitance in a region where a functional cell (logic gate cell) is not located.
Generally, the capacitor in the semiconductor integrated circuit is often constituted of a field effect transistor (hereinafter, FET). Specifically, electrically connecting the source terminal and drain terminal of the FET as shown in FIG. 5 enables utilizing the gate electrode, the gate insulating layer and the channel region of the FET as the upper electrode, the capacitance insulating layer and the lower electrode capacitor of the capacitor, respectively. Here, the FET in FIG. 5 is provided between a power source (VDD) and a ground (GND), so as to act as a decoupling capacitance.
Also, Japanese Laid-open patent publication No. 2001-44283 discloses a semiconductor integrated circuit including a fill-cell in which a fill-cell resistance is provided.
In the capacitor constituted of the FET, however, the path from the channel region (lower electrode) to the source/drain region has a high electrical resistance. This path is where a charge flowing into and out of the lower electrode runs through. The high electrical resistance in this path, therefore, leads to degradation in frequency response of the capacitor.
From the viewpoint of improving the frequency response, reducing the length of the gate electrode (gate length) would be a solution. In this case, however, the electrode area of the capacitor is inevitably reduced, which incurs another problem that the capacitance value is decreased.